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- 1. A standard TTL gate performs what logic function for positive logic? 2. If all inputs of a TTL gate are binary 1, the output will be 3. The typical TTL logic levels are: Binary 0= 4. MOS combining both P- and N-channel in series is called 5. The CMOS logic levels are: binary 0 = volts and binary 1 = volts. volts and binary 1 = ______ volts.d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.For the basic TTL gate shown in figure (5), if all the inputs are high at logic (1), BR = 0.02 and Br = 100, then find the value of: Note: (Write the equations of each point not just the value) 1) IB2 = Amperes. 2) Vc2=1 3) Ic2= Amperes. 4) IIKQ = 5) IB3 = Amperes. 6) Ic3 = Amperes. Volt. Amperes. Figure (5) 1.4k 4k 0₂ Y
- 1E. Write a VHDL code for all Logic Gates and verify Output waveforms. 2E. Write a VHDL code for Half Adder and verify Output waveforms. 3E. Write a VHDL code for Full Adder and verify Output waveforms.4) Draw a logic diagram of a divide-by-14 counter using IC 7493 and 2-input AND gate.A d. B Figure 1 3. Referring to the logic circuit in Figure 1, determine: a. The simplified Boolean expression. b. The output waveform. C H c. Due to fabrication errors, lines d and f were shorted to the supply voltage. What happens to the output of the circuit? d. Your hardware resources are limited to 2-input NOR gate only. Draw the gate schematic of the simplified Boolean expression in 3(a).
- Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- Cin Cout Figure Q4(a)(ii)Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- B Cin Cout Figure Q4(a)(ii) (iii) Given A = 111001 and B = 100010. Construct a 6-bit parallel adder to solve for A + B.Figure 4 shows the decimal to BCD encoder logic. Assume that the 9 input and 3 inputare both HIGH.i) Determine the output code.ii) Is the value valid for BCD (8421) code?
- Q1) For the circuits shown in figures 1 and 2: 1. What is the function of output? 2. Find the max. and min. Vol. value? 3. Determine the static power (avg.)? 4. Design equivalent logic circuit by CMOC logic circuits? Use VDD= 10 V. Vr.o=1V. Vru-1V. (W/L)o= (5/2), (W/L)L (20/2), RD = 40k, KL = 10P A/V^2 and KO = 40pA/V`2? Figure 1 5 VDD RD Figure 2 बदना दे1. Write the TTL level of the following voltages (low, high, intermediate). 2.5 . 0.3 . 4.6 . 1.1.. 3.2. ........ 2. .are complete circuits constructed on a chip of semiconductor material. What is the 3 common types of integrated circuits? . describes data shifted manually, .. describes data shifted automatically for 8 bit shift register. 3. How serial and parallel data shifted into 8 bit shift register?Draw the logic diagram and transistor implementation for a (2-2-2) AOI.