1. Solve the following problems: a) Given a 50 MHz FOSC, how long does it take the instruction goto done to execute in nanoseconds? b) Given a 40 MHz FOSC, how long does it take the instruction mov W2, W4 to execute in nanoseconds? c) How many add W0, W1, W2 instructions are executed in 1 second assuming a 50 MHz FOSC?
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A: Answer: I have given answer in the brief explanation.
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A: According to the information given:- we have to execute the instruction sequence
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A: The answer is...
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A: (a)Non-pipelined single-processor machineAverage CPI = (0.25*2 + 0.3*10 + 0.15*4 + 0.3*1.5) = 4.55
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A: Below is the answer to above question. I hope this will be helpful for you.
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A: Solution is given below:-
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A: Given:
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A: the answer is....
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A: Solution Given , DS=100H SS=2000H BP=200H SI=0100H BX=1500H Instruction is : MOV AL , [ BX + 500 ]
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A: the option c is correct
Q: 3-Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions,…
A: The answer is...
Q: 3-Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions,…
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Q: Address Word Ox00000015 ? Ox00000014 ? Ox00000013 ? Ox00000012 ? Ox00000011 )x00000010
A: Here is the solution to the above problem: -
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A: Answer: I have given answered in the handwritten format in brief explanation
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A: The Time taken for n number of instructions which are of normal type= n*CPI/(clock rate)
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A: *As per the company norms and guidelines we are providing one question answer only please repost…
Q: 3-Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions,…
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A: solution for the above question is solved in step 2:-
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Q: Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions, 80…
A:
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- A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?A microprocessor scans the status of an output I/O device every 20 ms. This is accom- plished by means of a timer alerting the processor every 20 ms. The interface of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 8 MHz? Assume for sim- plicity that all pertinent instruction cycles take 12 clock cycles.
- Assume for a given program, 60% of the executed instructionsare of Class A, 10% are of Class B, and 30% are of Class C. Furthermore,assume that an instruction in Class A requires 3 cycles, an instruction inClass B requires 2 cycles, and an instruction in Class C requires 2 tocomplete. i. Compute the overall CPI for this program.ii. Compute the clock rate of the CPU when the time it takes tocomplete 20 instructions is 1.73 ???????????Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions, 80 × 106 L/S instructions, and 16 × 106 branch instructions. The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. By how much must we improve the CPI of FP instructions if we want the program to run two times faster? By how much must we improve the CPI of L/S instructions if we want the program to run two times faster? By how much is the execution time of the program improved if the CPI of INT and FP instructions is reduced by 40% and the CPI of L/S and branch is reduced by 30%? (FP: Floating Point, INT: Integer, L/S: Load Store)B. For the following 8085 assemble code, calculate the total execution time 0100: LXI 0103: MVI C,0 0105: NOP 0106: NOP 0107: DER C D,1000H 0108: JNZ 0105H 010A: MOV A,M 010B: OUT 05H SKIP : C. what is the single instruction equivalent to the following code: XOR DX,DX TEST AX,8000H JZ NOT Total execution time = SKIP DX
- Assume for arithmetic, load/store, and branch instructions, a processor has CPIs of 1, 12, and 5, respectively. Also assume that on a single processor a program requires the execution of 2.56E9 arithmetic instructions, 1.28E9 load/store instructions, and 256 million branch instructions. Assume that each processor has a 2 GHz clock frequency. Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor is divided by 0.7 x p (where p is the number of processors) but the number of branch instructions per processor remains the same. Find the total execution time for this program on 1, 2, 4, and 8 processors, and show the relative speedup of the 2, 4, and 8 processor result relative to the single processor result. If the CPI of the arithmetic instructions was doubled, what would the impact be on the execution time of the program on 1, 2, 4, or 8 processors? To what should the CPI of load/store instructions be…Given the RISC instruction xorcc %i1, 885, %g4 Answer the following questions regarding the 32-bits of this instruction (all answers should be binary one's and zero's and should NOT contain any spaces): a) What are the two most significant bits of this instruction? b) What are the five destination register bits? c) What are the six operation bits? d) What are the five first operand bits? e) What is the value of bit 13? f) What are the second operand bits stored in instruction bits 12 down to 0? (must be appropriate size in binary)Two processors A and B have clock rate of 700 MHz and 900 MHz respectively. Suppose A can execute an instruction with an average CPI equal to 3 and B can execute with an average CPI of 5. For the execution of same instruction, which processor is faster? Select one: a. Both are equally fast O b. B c. None O d. A
- Continuing with a 32 Khz system clock/8000 Khz instruction clock, assuming a pre-scalar of1:2 (i.e. no prescalar), and 16-bit operation, if TMR0 is initialized to 64536, how many timeswill TMR0 need to be incremented before it overflows?72. How many instructions cycles will that take?Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 5.1 GHz clock rate and a CPI of 0.33. P2 has a 4.9 GHz clock rate and a CPI of 1.94. P3 has a 3.9 GHz clock rate and a CPI of 1.96. (a) How many instructions per second can each processor execute? (b) If the processors each execute a program in 60 seconds, find the number of cycles and the number of instructions of the program. (c) Suppose we implement an architectural optimization on P3 which reduces the CPU time by 14% but leads to an increase of 8% in the CPI. What is the new clock rate?On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?