1.14 Assume a program requires the execution of 50 x 106 FP instructions, 110 x 106 INT instructions, 80 x 106 L/S instructions, and 16 x 106 branch instructions. The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. 1.14.1 (10] <$1.10> By how much must we improve the CPI of FP instructions if we want the program to run two times faster? wa impro of I (S inctruc
Q: Assume X address is 29D, find the value of AX for each of the following instruction .Data X byte 12,…
A: Given:
Q: Q13/Assume that the microprocessor can directly address 64K with a and 8 data pins The memory map…
A:
Q: Assume that you have a A= 5x5 Matrix with one byte size elements.. Write an Assembly program that…
A: Required:
Q: An integer array [119,117,17,64] is stored in memory. Each integer has 32 bits. Suppose the first…
A: .dataArray : .word 68,251,88,204,126.globl main.textmain:#load index of arrayla $t9,Arrayli $t0,0…
Q: Part(c) : Assume a hypothetical system with eight 32-bit words cache and small Main memory of 1 KB…
A: the solution of part c is given below :
Q: Exercise 4: Self-modifying programs - Full Uniformity li $t0, 9 li $t1, 9 blt $t0, $t1, less la $a0,…
A: 1.Yes. We can reorder the instructions, which allows us to execute program in fewer clock cycle. In…
Q: 4. In this question, we consider the relative performance obtained by running a particular with…
A: Answer is given below .
Q: .CLO2.3: Consider the instruction formats of the basic computer given in class. For the following…
A: please see the next step for solution
Q: 2.10 Consider the following program: int x = 0, y = 0; co x = x + 1; x = x + 2; // x = x + 2; y = y…
A:
Q: Q1/ Two word - wide unsigned integers are stored at the physical memory addresses 0400H and 0402H…
A: 1.mov 3 to eax and mov 4 to ebx and also use mul ebx to put 12 in eax2. now mov eax to ecx to…
Q: Suppose the implementation of an instruction set architecture uses three classes of instructions,…
A: Intro Suppose the implementation of an instruction set architecture uses three classes of…
Q: 9- 1. Assume that 8086 Microprocessor segment registers are DS: 1000H CS: 2000H Which of the…
A: Here is the explanation about the question:
Q: 3- Let a program have a portion fr of its code enhanced to run 4 times faster, to yield a system…
A: In this question, we are given enhanced speedup(SE) and overall speedup of system. And we are asked…
Q: Problem 1.8 The following code segment, consisting of six instructions, needs to be executed 64…
A:
Q: Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store…
A: Hence, It is NOT a good choice. I Type I Count (M) CPI Cycles Arithmetic 375 1 375…
Q: Consider the following high-level function. int f(int n, int k) { int b; b = k + 2; if (n == 0) b =…
A: ANSWER:-
Q: PROBLEM-3: Consider the following code fragment to be executed inanstage pipeline machine resolved…
A: Answer: Our instruction is answer the first three part from the first part and . I have given…
Q: Consider the 2-address instruction SUB R1, X which subtract the contents of location X from the…
A: Overview : In computer central processing units, micro-operations (also known as micro-ops) are the…
Q: 12. Consider the following instruction: Instruction: AND Rd,Rs,Rt Interpretation: Reg[Rd] = Reg[Rs]…
A: The question is on choosing the correct option from the given options considering the given…
Q: In the typical five stages of MIPS, which type of instruction actually does active work in each and…
A: Answer: Given some instruction and we need to identify the which one ids more suitable for given…
Q: Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3…
A: In Assembly language : al is the lower 8 bits ah is the higher 8 bits Mov is the instruction used…
Q: 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 1.…
A: Introduction A piece of electronic information stockpiling gadget incorporated into the recording…
Q: 10. Consider the following code: .386 .model flat, stdcall .stack 4096 ExitProcess PROTO,…
A: the solution is given below :
Q: Q2. A. Define the content of registers and/or Memory location after executing each instruction in a…
A: 1)Mov Ax, 33 H P. A= DS × 10H + [33H] = 200H × 10H +33H = 2000H +33H P. A…
Q: 9. If we have AX-8A3C H, CL-02 H. the result of performing SAL AX,CL is: a. C51E H c. 451E H b. E28F…
A: Answer 9) in the question option is not right the correct answer is: 28F0. explanation:
Q: Answer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program…
A:
Q: Problem4: A microcomputer has the following memory map: 4100 to 410F I/O 2100 to 22FF RAM 0000 to…
A:
Q: What is result of executing the following instruction sequence? MOV BX, 100H MOV [ BX], 0C0ABH MOV…
A: Answer:
Q: 5-Consider a computer running a program that requires 400 s, with 80 s spent executing FP…
A: Solution: Given, Total time = 400s FP (Floating point) = 80s L/S (Load / Store) = 40s Branch B = 40s
Q: 3. Assume $s1 = 0xefbcad97, $s2 = 0x6521fedc, calculate and $s0,$s1,$s2 or $s0,$s1,$s2 xor…
A: Here is the answer:-
Q: Question 1: Write down the corresponding MIPS machine language of the following assembly language…
A: Given: Question 1: Write down the corresponding MIPS machine language of the following assembly…
Q: Consider a program that declares global integer variables x, y[10]. Thesevariables are allocated…
A: Explanation of the code: lw $s1, 0($gp) #load value in base address to $s1addi $s1, $s1, 25…
Q: 1. Assume that 8086 Microprocessor segment registers are DS: 1000H CS: 2000H 2- Which of the…
A: Given:
Q: Question 2 Consider the following fragment of C code: for (i=0; i<100; i++) { A[i] =B[i]+C; } Assume…
A: MIPS CODE for the above code mentioned: DADD R1, R0, R0 ; R0 = 0; initialise i = 0 SW R1, 7000(R0);…
Q: 5. Consider an integer array x, initialized with 8 decimal values. After running this instruction…
A: [Note - Hello. Since your question has multiple parts, we will solve first question for you. If you…
Q: 4. A computer has a 5-stage instruction pipeline of one cycle each. The 5 stages are: Instruction…
A: ANSWER:-
Q: For each of the following page replacement policies, list the total number of page faults and fill…
A: Answer:a. LRU replacement:
Q: Loop1 MOVLW 0x32 MOVWF REG2 DECFSZ REG2,F GOTO LOOP1 If the system clock frequency is aMHz and each…
A: Hey there,I am writing the required solution for the above mentioned question below.
Q: Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size…
A: D) Total number of virtual memory bits to be translated is V bits.
Q: Prog1 request 80KB, prog2 request 16KB, Prog3 request 140KB Prog1 finish, Prog3 finish; Prog4…
A: Memory Memory is the electronic holding place for the instructions and data of a computer needs to…
Q: Consider the following instruction: Instruction: Add Rd, Rs, Rt Interperation: Reg[Rd] = Reg[Rs] +…
A: ALUMux: It is signal that controls the multiplexer from the input of ALU, with the binary values 0…
Q: Suppose the implementation of an instruction set architecture uses three classes of instructions,…
A: Suppose the implementation of an instruction set architecture uses three classes of instructions,…
Q: Q.4 CO4 Consider a hypothetical computer having instruction length 32 bit and Byte addressable…
A: We are given a processor whose instruction length is 32-bit and it is byte addressable memory.…
Q: 1. Consider a machine running a program with four classes of instructions: A/B/C/D. The program…
A:
Q: Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store…
A: Initial CPl = 10×300900+1×500900+3×100900 =309+59+39= 389=4.221) New no. of…
Q: 1. Verify each instruction starts from these values: AL = 85H , BL = 35H a) MUL BL b) IMUL BL c) DIV…
A: This Question comes from the portion of Control and systems from microprocessor all the given…
dont post copied answers
answer only 100% sure
otherwise dislike and report answer
Trending now
This is a popular solution!
Step by step
Solved in 2 steps
- Assume that a program requires the execution of 125x106 FP (floating point) instructions, 130x106 INT (integer) instructions, 150x106 L/S (load/store) instructions, and 110x106 branching instructions. These instructions have CPIs of 1, 1, 8 and 4, respectively. Assume that the processor has a 5 GHz clock rate. a. Is it possible to run the program twice as fast if we improve the CPI of just the L/S instructions? If so, by how much? Show your calculations. b. What is the Speedup in the execution time of the entire program if the CPI of INT and FP instructions is reduced by 40% and that of L/S and branching instructions is reduced by 50%?5-Consider a computer running a program that requires 400 s, with 80 s spent executing FP instructions, 40 s executed L/S instructions, and 40 s spent execut- ing branch instructions. • By how much is the total time reduced if the time for FP operations is reduced by 5%? • By how much is the time for INT operations reduced if the total time is reduced by 5%? • Can the total time can be reduced by 10% by reducing only the time for branch instructions?1. Consider a machine running a program with four classes of instructions: A/B/C/D. The program requires 360 seconds, with the number of seconds executing each class as shown in the table below: Instruction Class A B C Time (sec) 100 80 120 60 1.1. By how much is the total execution time changed if the time for class D is reduced by 20% and the time for class C is increased by 10% (assuming no other changes)? 1.2. If we want to reduce the total execution time by 20% by optimizing class A only, what is the target execution time of class A instructions in order to achieve the reduction (assuming all other instructions are not changed)? 1.3. Can the total time be reduced by 25% if we only optimize class B? Use calculation to justify your answer.
- Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions, 80 × 106 L/S instructions, and 16 × 106 branch instructions. Th e CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. By how much must we improve the CPI of FP instructions if we want the program to run two times faster? By how much must we improve the CPI of L/S instructions if we want the program to run two times faster? By how much is the execution time of the program improved if the CPI of INT and FP instructions is reduced by 40% and the CPI of L/S and Branch is reduced by 30%?2.1 A benchmark program is run on a 40 MHz processor. The executed program consists of 100,000 instruction executions, with the following instruction mix and clock cycle count: Instruction Type Instruction Count Cycles per Instruction Integer arithmetic 45,000 1 Data transfer 32,000 Floating point 15,000 Control transfer 8000 Determine the effective CPI, MIPS rate, and execution time for this program.Q1: Consider two computers, P1 and P2, of the same instruction set (ISA). We have a program of 7.5x10° instructions and we want to run this program on P1 and P2. The P1 computer is a 5 GHz machine with CPI of 0.8. The P2 computer is a 6 GHz machine with CPI of 1.2. Which computer is faster?
- one Mil Q#1: Consider the instruction: add $2, $1, $3 What registers will be written and what registers will be read to execute this instruction? Registers to be written Registers to be read Q#2: Since we only support the add instruction, we don't care much for opcodes and funct codes and shamts. Therefore, suppose our programs are given to the processor as three inputs RD, RS, and RT. Each instruction executes within 1 clock periods Translate the following program to the RW, RS, RT inputs (in binary). clock period RD RS 1 2 3 4 RS RT Program add $2, $1, $3 add $0, $0, $1 add $1, $2, $2 add $1, $1, $1 Q#3: Design the single-cycle cessor datapath (only ID, EX and WB stages) using the mong different components. following datapath components.rly s the number of bits to be transferred in each data line and data bus connectio RD cik Registers RA RB RW BusA RegWrite Bus8 Bus W ALU zero ALU result overflow RT ALUOPConsider a hypothetical computer having instruction length 32 bit and Byte addressable memory. You need to run a program P having 10 Q.4 CO4 instructions 11,12,13...10. All the instructions are stored in consecutive memory locations started from 1000. To run an instruction li, you have to complete four operations: Fetch, Decode, Execute, and Store. The content of Program Counter will be after the completion of fetch operation of instruction 12. There are no jump or branch instruction in program PQ1. Compute the effective CPI for an implementation of a RISC-V CPU using The Figurel. Assume we have made the following measurements of average CPI for instruction types: Instruction All ALU operations Loads Stores Branches Jumps Program astar bzip gec gobmk h264ref hmmer libquantum mcf omnetpp perlbench sjeng xalancbmk Loads 28% 20% 17% 21% 33% 28% 16% 35% 23% 25% 19% 30% Stores 6% 7% 23% 12% 14% 9% 6% 11% 15% 14% 7% 8% Clock cycles 1.1 4.2 3.3 2.8 3.0 Branches 18% 11% 20% 14% 5% 17% 29% 24% 17% 15% 15% 27% Jumps 2% 1% 4% 2% 2% 0% 0% 1% 7% 7% 3% 3% ALU operations 46% 54% 36% 50% 45% 46% 48% 29% 31% 39% 56% 31% Average the instruction frequencies of astar and perlbench to obtain the instruction mix.
- 1A. Consider the following code: AREA ASCENDING, CODE, READONLY ENTRY MOV R8, #2 LOOPO LDR R1, [R2], #4 STR R1, [R3], #4 SUBS R8, R8, #1 CMP R8, #0 BNE LOOPO How many clock cycles are required to complete the execution of the above code on non- pipelined processor assuming each instruction will take 1 cycle to execute completely? Show calculations. How many clock cycles required to complete the execution of the above code on 3-staged pipelined processor? Draw the pipeline diagram for the same. Let one stage requires one clock cycle and assume all memory references hit in cache.Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions, 80 × 106 L/S instructions, and 16 × 106 branch instructions. The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. By how much must we improve the CPI of FP instructions if we want the program to run two times faster? By how much must we improve the CPI of L/S instructions if we want the program to run two times faster? By how much is the execution time of the program improved if the CPI of INT and FP instructions is reduced by 40% and the CPI of L/S and branch is reduced by 30%? (FP: Floating Point, INT: Integer, L/S: Load Store)Q13. A program has the following mix of instructions: Instruction Cycles Frequency 33% 17% 17% 33% Load Store Branch Arithmetic 2 2 6 1 What is the average number of clock cycles per instruction (CPI) for this program? A. 0.11 B. 9.09 C. 2.75 D. 2.35 E. 21.36