4. FIGURE 1 shows how a 3 to 8 line decoder (TTL 74138) can be used in conjunction with NAND gate (TTL 74133) to connect a set of switches to the data bus of a microprocessor system via buffers (TTL 74367). Answer the following questions relating to the diagram: a) What address, in HEX, is required on the address bus in order toread the switches? b) RD and MEMRQare control lines from the CPU. What must their logic state be in order to read the switches?

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