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4. For your code in the previous problem, microprocessors require the following amounts of time to fetch, decode and execute each instruction. Which microprocessor calculates X the fastest? Instruction Type Microprocessor Microprocessor #0 Microprocessor #1 Microprocessor #2 Microprocessor #3 Time per instruction 0-operand instructions 1-operand instructions 2-operand instructions 3-operand instructions 48 ns 60 ns 80 ns 120 ns

4. For your code in the previous problem, microprocessors require the following amounts of time to fetch, decode and execute each instruction. Which microprocessor calculates X the fastest? Instruction Type Microprocessor Microprocessor #0 Microprocessor #1 Microprocessor #2 Microprocessor #3 Time per instruction 0-operand instructions 1-operand instructions 2-operand instructions 3-operand instructions 48 ns 60 ns 80 ns 120 ns

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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3. Show the code to perform the computation X = A + (B + C) * D * E using microprocessors which use the instruction formats shown below. Each microprocessor has ADD and MUL instructions in its instruction set. Do not modify the values of A, B, C, D and E. If necessary, use temporary location T to store intermediate results. a) 3-operand instructions b) 2-operand instructions c) 1-operand instructions d) 0-operand instructions Step 2 Solution: X = (Ax B) + (CX (D+ E)) compute using Zero,0ne,Two,Three operand(Address) Instructions a.3-Operand Instructions for X = (Ax B) + (CX (D+ E)) Code Description R1 <--A * B ( Multiplication of operands A,B) where R1 is Temporary Register to store result MUL R1,A,B ADD R2, D,E R2 <--D +E ( Addition of Operands D,E) and R2 is another Temporary Register to store result MUL R2, R2,C R2 <-- R2* C ( Multiplication of operands R2,C) where R2 is Temporary Register to store result ADD X, R1,R2 X<-R1 + R2 ( Here R1 already contains A *B and R2 Contains (C * (D + E))
Transcribed Image Text:3. Show the code to perform the computation X = A + (B + C) * D * E using microprocessors which use the instruction formats shown below. Each microprocessor has ADD and MUL instructions in its instruction set. Do not modify the values of A, B, C, D and E. If necessary, use temporary location T to store intermediate results. a) 3-operand instructions b) 2-operand instructions c) 1-operand instructions d) 0-operand instructions Step 2 Solution: X = (Ax B) + (CX (D+ E)) compute using Zero,0ne,Two,Three operand(Address) Instructions a.3-Operand Instructions for X = (Ax B) + (CX (D+ E)) Code Description R1 <--A * B ( Multiplication of operands A,B) where R1 is Temporary Register to store result MUL R1,A,B ADD R2, D,E R2 <--D +E ( Addition of Operands D,E) and R2 is another Temporary Register to store result MUL R2, R2,C R2 <-- R2* C ( Multiplication of operands R2,C) where R2 is Temporary Register to store result ADD X, R1,R2 X<-R1 + R2 ( Here R1 already contains A *B and R2 Contains (C * (D + E))
4. For your code in the previous problem, microprocessors require the following amounts of time to fetch, decode and execute each instruction. Which microprocessor calculates X the fastest? Instruction Type Microprocessor Microprocessor #0 Microprocessor #1 Microprocessor #2 Microprocessor #3 Time instruction per 48 ns 0-operand instructions 1-operand instructions 2-operand instructions 3-operand instructions 60 ns 80 ns 120 ns
Transcribed Image Text:4. For your code in the previous problem, microprocessors require the following amounts of time to fetch, decode and execute each instruction. Which microprocessor calculates X the fastest? Instruction Type Microprocessor Microprocessor #0 Microprocessor #1 Microprocessor #2 Microprocessor #3 Time instruction per 48 ns 0-operand instructions 1-operand instructions 2-operand instructions 3-operand instructions 60 ns 80 ns 120 ns
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