A computer with a 32-bit 3.5 gigahertz scalar non- pipelined CPU needs to invert the colors of a 150 KB bitmap image file located in the RAM. To do this, each bit of the image must be complemented (Os are converted to 1s and vice-versa). Assume every instruction undergoes the following stages and each stage uses one CPU clock cycle: Fetch • Decode . Read from memory • Execute • Write to memory Instructions: For this assignment, you must calculate how much time the computer will need to invert the image with a single-core and a dual core CPU. Show and explain your calculations and assumptions in a short paper and answer the following questions: . Will there be any parallel slowdown? Why or why not? Length: 2-3 page explanatory paper

A computer with a 32-bit 3.5 gigahertz scalar non- pipelined CPU needs to invert the colors of a 150 KB bitmap image file located in the RAM. To do this, each bit of the image must be complemented (Os are converted to 1s and vice-versa). Assume every instruction undergoes the following stages and each stage uses one CPU clock cycle: Fetch • Decode . Read from memory • Execute • Write to memory Instructions: For this assignment, you must calculate how much time the computer will need to invert the image with a single-core and a dual core CPU. Show and explain your calculations and assumptions in a short paper and answer the following questions: . Will there be any parallel slowdown? Why or why not? Length: 2-3 page explanatory paper

Name: A computer with a 32-bit 3.5 gigahertz scalar non-pipelined CPU needs
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Description: A computer with a 32-bit 3.5 gigahertz scalar non-pipelined CPU needs to invert the colors of a 150 KBbitmap image file located in the RAM. To do this, eachbit of the image must be complemented (Os areconverted to 1s and vice-versa).Assume every ins

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Question 6 Suppose you have a RISC machine with a 1.6 GHz clock (i.e., the clock ticks 1.6 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: set reg, immed 2 clock cycle 2 clock cycles 2 clock cycle 4 clock cycles 3 clock cycles loop label add reg, immed add reg, reg load reg, mem Assume that the following code franent is used to sum the element of a numeric array. If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in 5 ms? Round your answer to the nearest integer. Recall that 1 ms = 0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired. ri, e r2, MAX_SIZE ;initialize loop counter r3, @list initialize sum set set set initialize array pointer more: load…
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A digital computer has a memory unit with 32 bits per word. The instruction set consists of 110 different operations. All instructions have an operation code part (opcode) and two address fields: one for a memory address and one for a register address. This particular system includes eight general-purpose, useraddressable registers. Registers may be loaded directly from memory, and memory may be updated directly from the registers. Direct memory-to-memory data movement operations are not supported. Each instruction is stored in one word of memory.1. a) How many bits are needed for the opcode?2. b) How many bits are needed to specify the register?3. c) How many bits are left for the memory address part of the instruction? d) What is the maximum allowable size for memory?5. e) What is the largest unsigned binary number that can be accommodated in one word of memory?
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