estion 2. Answer the below questions. a. Consider a FSM with 11 states. How many bits are needed to represent each state uniquely? Mention the steps.

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Question 2.
Answer the below questions.
a. Consider a FSM with 11 states. How many bits are needed to represent each state
uniquely? Mention the steps.
b. Consider the below partial Verilog code for a FSM. Explain in detail how it works. What
happens if a negative edge of the craaod positive edge of the clk signal happen at the
same time and why?
1 always @(negedge clr_, negedge clk)
2 if(!clr_ ) y<=s0;
else y <=Y;
Transcribed Image Text:Question 2. Answer the below questions. a. Consider a FSM with 11 states. How many bits are needed to represent each state uniquely? Mention the steps. b. Consider the below partial Verilog code for a FSM. Explain in detail how it works. What happens if a negative edge of the craaod positive edge of the clk signal happen at the same time and why? 1 always @(negedge clr_, negedge clk) 2 if(!clr_ ) y<=s0; else y <=Y;
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