C D. A B D. D E E' A' B' C' CLK (a) Four-stage switch-tail ring counter Flip-flop outputs Sequence number AND gate required for output A B E A'E' AB' 1 1 1 BC' 1 1 1 CE' 1 1 1 1 1 AE 1 1 1 0 0 A'B 1 B'C СЕ (b) Count sequence and required decoding FIGURE 6.18

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
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Write and verify the HDL description of a four-bit switch-tail ring (Johnson) counter (Fig. 6.18a).

C
D.
A
B
D.
D
E
E'
A'
B'
C'
CLK
(a) Four-stage switch-tail ring counter
Flip-flop outputs
Sequence
number
AND gate required
for output
A
B
E
A'E'
AB'
1
1
1
BC'
1
1
1
CE'
1
1
1
1
1
AE
1
1
1
0 0
A'B
1
B'C
СЕ
(b) Count sequence and required decoding
FIGURE 6.18
Transcribed Image Text:C D. A B D. D E E' A' B' C' CLK (a) Four-stage switch-tail ring counter Flip-flop outputs Sequence number AND gate required for output A B E A'E' AB' 1 1 1 BC' 1 1 1 CE' 1 1 1 1 1 AE 1 1 1 0 0 A'B 1 B'C СЕ (b) Count sequence and required decoding FIGURE 6.18
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