Consider a two level cache system. For 100 memory references, 20 misses in the first lyel cache and 6 miss in the second level cache. Miss penalty from L, cache to memory is 40 cycles. The access time of L, cache is 4 cycles and access time of the L, cache is 1 clock cycle. What is the average memory access time (in cycle)?

Consider a two level cache system. For 100 memory references, 20 misses in the first lyel cache and 6 miss in the second level cache. Miss penalty from L, cache to memory is 40 cycles. The access time of L, cache is 4 cycles and access time of the L, cache is 1 clock cycle. What is the average memory access time (in cycle)?

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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