Consider the circuit in Figure Q.7(i) UTM US UTM& UTM UTM UTM O UTM UTM U TM UTM UTM UTM UTM Figure Q.7(i) UTM UTM 3 UTM UTM UTM UTM TITM 증 UTM UTM UTM G UTM ITM 6 UTM ITM O UTM 10

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7.
Consider the circuit in Figure Q.7(i)
UTM UTM 3
DaD
o UTM UTM
UTM UTM 3 UTM
UTM &UTM U TM UTM 8 UTM
UTM 1
6 UTM UTM 3 UTM
Figure
UTM UTM 5 UTM
UTM O UTM
UTM U
UTM UTM UTM
ITM O UTM
UTM U
ITM O UTM
3
SEEE/SEEU 1223
UTM UTM UTM
UTM UTM UTM
7(a)F
UTM
8 UTM
UTM L
UTM UT UTM
UTM
8 UTM
6 UTM & UTM VIM
UTM U
UTM UM GÚTM
(ii) If W is always connected to HIGH input, determine the new output
Draw the timing waveform of output 7(a)F if input W, X and Y
are as shown in Figure Q.7(ii).
3 UTM UO , UTM
Figure Q.7(ii)
O UTM OU
UTM
(iii) If you have to replace the XOR gate with other basic gate, what is
UTM
the suitable gate for you to use so that your output from 7(b)F
is maintained.
JTM
WTM UTM
UTM
JTM UTM
------
Transcribed Image Text:7. Consider the circuit in Figure Q.7(i) UTM UTM 3 DaD o UTM UTM UTM UTM 3 UTM UTM &UTM U TM UTM 8 UTM UTM 1 6 UTM UTM 3 UTM Figure UTM UTM 5 UTM UTM O UTM UTM U UTM UTM UTM ITM O UTM UTM U ITM O UTM 3 SEEE/SEEU 1223 UTM UTM UTM UTM UTM UTM 7(a)F UTM 8 UTM UTM L UTM UT UTM UTM 8 UTM 6 UTM & UTM VIM UTM U UTM UM GÚTM (ii) If W is always connected to HIGH input, determine the new output Draw the timing waveform of output 7(a)F if input W, X and Y are as shown in Figure Q.7(ii). 3 UTM UO , UTM Figure Q.7(ii) O UTM OU UTM (iii) If you have to replace the XOR gate with other basic gate, what is UTM the suitable gate for you to use so that your output from 7(b)F is maintained. JTM WTM UTM UTM JTM UTM ------
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