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Consider the following memory layout of three processes: Process A, Process B, and Process C. For simplification, we assume no use of virtual memory; thus, all three processes are represented by programs that are fully loaded in main memory as shown below. In addition, there is a small dispatcher program that switches the processor from one process to another. Address Main Memory 0 1000 6000 10000 16000 20000 30000 38000 Dispatcher Process A Process B Process C The following table shows the traces of each of the processes during the early part of their execution. The first 8 instructions executed in processes A and B are shown. Process C executes 3 instructions, and we assume that the 3rd instruction invokes an I/O operation for which the process must wait for 3 instruction cycles for the I/O operation to be completed. Trace of Process A 10,000 10,001 10,002 10,003 10,004 10,005 10,006 10,007 Trace of Process B 20,000 20,001 20,002 20,003 20,004 20.005 20,006 20,007 Trace of Process C 30,000 30,001 30,002 35,000 35,001 35,002 35,003 Trace of Dispatcher 1,000 1,001 1,002 1,003 Assume the following sequence of process execution: A8⇒CAB→ C. Draw these traces from the processor's point of view assuming that the OS only allows a process to continue execution for a maximum of 4 instruction cycles, after which it is interrupted to prevent any single process from monopolizing processor time. b) Draw the process states for the traces that illustrate the transition of each process among the states based on the Five-State Process Model. Process A Process C Dispatcher UnibetleL 10 15 20 25 30 Running - Ready ***for convenience, the instruction cycles are numbered - Blocked- Poto 40 45 50

Consider the following memory layout of three processes: Process A, Process B, and Process C. For simplification, we assume no use of virtual memory; thus, all three processes are represented by programs that are fully loaded in main memory as shown below. In addition, there is a small dispatcher program that switches the processor from one process to another. Address Main Memory 0 1000 6000 10000 16000 20000 30000 38000 Dispatcher Process A Process B Process C The following table shows the traces of each of the processes during the early part of their execution. The first 8 instructions executed in processes A and B are shown. Process C executes 3 instructions, and we assume that the 3rd instruction invokes an I/O operation for which the process must wait for 3 instruction cycles for the I/O operation to be completed. Trace of Process A 10,000 10,001 10,002 10,003 10,004 10,005 10,006 10,007 Trace of Process B 20,000 20,001 20,002 20,003 20,004 20.005 20,006 20,007 Trace of Process C 30,000 30,001 30,002 35,000 35,001 35,002 35,003 Trace of Dispatcher 1,000 1,001 1,002 1,003 Assume the following sequence of process execution: A8⇒CAB→ C. Draw these traces from the processor's point of view assuming that the OS only allows a process to continue execution for a maximum of 4 instruction cycles, after which it is interrupted to prevent any single process from monopolizing processor time. b) Draw the process states for the traces that illustrate the transition of each process among the states based on the Five-State Process Model. Process A Process C Dispatcher UnibetleL 10 15 20 25 30 Running - Ready ***for convenience, the instruction cycles are numbered - Blocked- Poto 40 45 50

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Consider the following memory layout of three processes: Process A, Process B, and Process C. For simplification, we assume no use of virtual memory; thus, all three processes are represented by programs that are fully loaded in main memory as shown below. In addition, there is a small dispatcher program that switches the processor from one process to another. Address Main Memory 0 1000 6000 10000 16000 20000 30000 38000 Dispatcher Process A Process B Process C The following table shows the traces of each of the processes during the early part of their execution. The first 8 instructions executed in processes A and B are shown. Process C executes 3 instructions, and we assume that the 3rd instruction invokes an I/O operation for which the process must wait for 3 instruction cycles for the I/O operation to be completed. Trace of Process A 10,000 10,001 10,002 10,003 10,004 10,005 10,006 10,007 Trace of Process B 20,000 20,001 20,002 20,003 20,004 20.005 20,006 20,007 Trace of Process C 30,000 30,001 30,002 35,000 35,001 35,002 35,003 Trace of Dispatcher 1,000 1,001 1,002 1,003 Assume the following sequence of process execution: A8⇒CAB→ C. Draw these traces from the processor's point of view assuming that the OS only allows a process to continue execution for a maximum of 4 instruction cycles, after which it is interrupted to prevent any single process from monopolizing processor time.
Transcribed Image Text:Consider the following memory layout of three processes: Process A, Process B, and Process C. For simplification, we assume no use of virtual memory; thus, all three processes are represented by programs that are fully loaded in main memory as shown below. In addition, there is a small dispatcher program that switches the processor from one process to another. Address Main Memory 0 1000 6000 10000 16000 20000 30000 38000 Dispatcher Process A Process B Process C The following table shows the traces of each of the processes during the early part of their execution. The first 8 instructions executed in processes A and B are shown. Process C executes 3 instructions, and we assume that the 3rd instruction invokes an I/O operation for which the process must wait for 3 instruction cycles for the I/O operation to be completed. Trace of Process A 10,000 10,001 10,002 10,003 10,004 10,005 10,006 10,007 Trace of Process B 20,000 20,001 20,002 20,003 20,004 20.005 20,006 20,007 Trace of Process C 30,000 30,001 30,002 35,000 35,001 35,002 35,003 Trace of Dispatcher 1,000 1,001 1,002 1,003 Assume the following sequence of process execution: A8⇒CAB→ C. Draw these traces from the processor's point of view assuming that the OS only allows a process to continue execution for a maximum of 4 instruction cycles, after which it is interrupted to prevent any single process from monopolizing processor time.
b) Draw the process states for the traces that illustrate the transition of each process among the states based on the Five-State Process Model. Process A Process C Dispatcher UnibetleL 10 15 20 25 30 Running - Ready ***for convenience, the instruction cycles are numbered - Blocked- Poto 40 45 50
Transcribed Image Text:b) Draw the process states for the traces that illustrate the transition of each process among the states based on the Five-State Process Model. Process A Process C Dispatcher UnibetleL 10 15 20 25 30 Running - Ready ***for convenience, the instruction cycles are numbered - Blocked- Poto 40 45 50
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