CSC 215 Exam 2 Name Fatema 1. Design a combinational circuit that converts a four-bit Gray code A, B, C, D (a binary numeral system where two successive values differ in only one bit, shown as table blow) to a bit four-binary number w, x, y, z. ABCD wxyz 0000 0000 0001 0001 0011 0010 4 0010 0011 0110 0100 4 0111 0101 g 0101 0110 6 0100 0111 1100 1000 1101 1001 1111 1010 1110 1011 1010 1100 1011 1101 b) Do the circuit (5 1001 1110 1000 1111 1x2 a) Using Karnaugh maps, obtain a minimum sum-of-products form w, x, y, and z. (20 points) 0:1 1.0 10 00 h map for W 92 92 90 2 9-21 10 O 0 0 D 0 ωχ 6.1. ド 0 1 1 1

We are provided an FP prototype labeled: IEEE 754-2015 of 15 bits similar to IEEE 754, where the exponent has size 6 bits and fraction has size 8 bits, and 1 MSB for the sign. No guard or round bits are assumed. What is the bias of the system? Find the smallest and largest number that can be represented. Find the new representation of the decimal number you worked with earlier (e.g., the 0.012).

(b) The bit strings for the sets {1,2,3,4,5} and {1,3,5,7,9} are 1111100000 and 1010101010, respectively. Use bit strings to find union, intersection and complement of both sets.

Consider a SEC code that protects 8-bit words with 4 parity bits. If we read the value0xABC, is there an error? If so, correct the error.Note: 0xABC = 1010 1011 1100Hint: Decode the 12-bit encoded data and find if there is an error.

Represent -53.625 using 32-bit IEEE-754 floating point standard. Indicate Sign bit (1 bit), Biased Exponent bits (8 bits), and Fractional bits (23 bits).  For the fractional bits, indicate just the first 9 bits out of 23. For example for 228 (slide 55 of chapter 5) your answer for the fractional bits would be 110010000.   sign bit --> biased exponent --> first 9 fractional bits -->

The Line Coding scheme that shows the best behavior (among the following) with a long sequence of ones (i.e. the bit 1) in terms of synchronization and baseline wandering is _____: Select one: a. Both NRZ-I and Unipolar NRZ b. Any of the mentioned choices are correct c. Both NRZ-L and NRZ-I d. Unipolar NRZ e. Bothe NRZ-L and Unipolar NRZ f. Polar NRZ-I g. Polar NRZ-L h. None of the mentioned choices is correct

271. In Return to Zero (RZ), the signal changes not between bits but a. before the bit b. after the bit c. doesn d. during the bit

a) Compute the even parity bits for the data bits: 1 1 0 1 0 1 1 1 and 1 0 0 0 1 0 1 0 b) Compute the odd parity bits for the data bits: 1 1 0 1 0 1 1 1 and 1 0 0 0 1 0 1 0 c) Transform the following bit string (D) into a 3 x 8 matrix and compute the two-dimensionaleven parity EDC bits. D = 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 d) Assume that a sender transmits <D, EDC> as shown and computed in c). Next, assume that thereceiver receives D’ and EDC’ as follows:D’ = 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 1; EDC’ = EDC, Does the received bit streamhave errors? If yes, how does the receiver detect or correct the errors and how many errors can bedetected or corrected?

In single precision (IEEE-754 standard), 8 bits are used for storing the exponent (the bias is 127), and 23 bits are used for storing the mantissa.  (a) What are the smallest and the largest positive numbers that can be stored in single precision? (b) What is the smallest value of the mantissa that can be stored?

For 7 bits floating point representation using: seeefff, what is the decimal value 0 111 100   Question 82 options:   A.  +NAN   B.  36   C.  3   D. 1/16   E. 1/8                     36.    Using a 6-bit cell  to store integers in 2's complement,  NOT  0 0 0 1 1 0 = ______?     A. 0 0 1  0 1 1   B.   0 1 0  1 0 0   C.  1 0 1 0 1 1   D. 0 0 1 1 0 0   E. 1 1 1 0 0 1