Design a combinational circuit, using the block diagram of Decoders and external gates to accept 2-bits number and generate an output binary number equal to the square of the input number.
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Q: - F
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- Q3) A - Convert the Excess-3 to binary number : ( 110001011100.10001010)ex-3 B- convert each Gray code to binary: 1-( 011010001001)G 2-(59)DThe numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True FalseAssume that the exclusive-OR gate has a contamination delay of 10 ns and that the AND or OR gates have a contamination delay of 5 ns. What is the total contamination delay time in the 8-bit adder? Note: your answer should include only the value of the delay without the unit (only the number) A B- Cin- Cout Answer:
- Design a combinational circuit with 3-inputs and 1-output. The output is equal to logic-1 when the binary value of the input is less than 3. And the output is logic-0 otherwise.Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)How to build this circuit? (on Digital or Logisim) Binary-coded decimal is an alternative method of representing integers using binary. In it, each base-10 digit is represented by four bits, thus each nibble takes one of 10 values (0000 through 1001). Therefore, using BCD, 42 (decimal) is represented as 0100 0010 (binary) and 196 (decimal) is represented as 0001 1001 0110 (binary). Create a circuit in Logisim that accepts as input a pair of two-digit integers represented as BCD and outputs their sum in BCD. Any and all Digital components are fair game. You can assume that all inputs will be valid BCD-encoded numbers.
- JOIN 3 circuits below(1,2 and 3) in a carry-ripple adder configuration and demonstrate binary addition of two three-bit numbers using a minimum of four number pairs that include both negative and positive numbers (signed 2s complement representation) and at least one overflow result. Circuit 1: a full-adder using any combination of gates from the following ICs: 7400, 7404,7408, 7410, 7420, 7432, and 7486 Circuit 2: a full-adder using a single 74138 IC and any additional assorted gates that may be necessary Circuit 3: a full-adder using a single 74138 IC and assorted gates.Electrical Engineering Draw 2, 1 bit ALUS to create a basic 2 bit ALU. the carry out and carry in bits must ripple across. The ALU should subtract/add, logical NOR, logical AND, and logical OR. Draw out the adding logic circuitQ2/Find the addition result for the following operation (66)8+ (1100)EX-3+(83)10-(F2.1)16 using 2's complement, assume that the result is binary number * 10011111.1111 None of them O 110000010.111 1111101.0001 O 1100000.0001
- Q2) convert the following: 1- decimal number to binary by using the repeated division by 2 method (49) 2- binary number to hexadecimal (10101010)( 3- octal number to decimal by repeated division by 8 method (254)() 4- BCD code numbers to decimal (100101111000)>() 5- Gray code to binary (1010)(Assume that the exclusive-OR gate has a contamination delay of 3 ns and that the AND or OR gates have a contamination delay of 2 ns. What is the total contamination delay time in the 4-bit adder? Note: your answer should include only the value of the delay without the unit (only the number) Note: Submit your work on paper as well А- B- Cin- Cout Answer:(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).