Design a simple ALU. There are 2 inputs. A and B, and each one is stored in 16-bit register and a 3-bit opcode. The output is a 17-bit register Y. The opcode controls ALU functions as follows: Opcode 000 001 010 011 100 101 110 Operation Y <= A Y <= A + B 111 Y <=A-B Y<=A AND B Y
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- (d) The table below shows the ALUcontrol signal of the datapath we discussed in class. Instruction Funct ALU Орсode ALUop ALU action operation field control Iw 00 load word XXXXXX add 0010 Sw 00 store word XXXXXX add 0010 beq 01 branch equal subtract 0110 XXXXXX R-type 10 add 100000 add 0010 R-type 10 subtract 100010 subtract 0110 R-type 10 AND 100100 AND 0000 R-type 10 OR 100101 OR 0001 R-type 10 set on less than 101010 set on less than 0111 You want to add the bne instruction into the datapath, which already includes the required hardware for the instruction. Write out the ALUop for bne and how you can determine whether the bne results in the branch to be taken.Design all operations of the ALU independently. There are a total of 8 operations. All operations are 4 bit. · F=A+B with Carry in and Carry out · F=B-A with Borrow In and Borrow out · F=A-B with Borrow In and Borrow out - F=2xAwith a flag for overflow - F=A/2 with a flag for overflow · F=AxB with overflow · F=AXORB (Bitwise XOR) · F= A< B (F = 1 if true, F=0 otherwise)Consider a microprocessor based board which has 7-segment and Led is connected to it. Design an assembly language code such that input from user is taken; when user presses “1” “AB9876543CDEF210” should display on 7-seg Display and when user press 2 leds should glow 17 times in a loop. If any other key is pressed no action should be taken Rubrics: Analytic Approach (50%) Syntax (25%) Desired output (25%)
- The instruction used to fill DX with the its sign bit is: * CWD SAR DX, 1 SAR DX, SF SHR DX, CL SHR DX, SF SAR DX, 10 SAR DX, [SF] SAR DX, 16D-Latch is a simple clocked memory element in which the output is equal to the stored state inside the element. In D-Latch the state is changed whenever the appropriate inputs change and the clock is asserted. A D-Latch has two inputs and two outputs. The inputs are the data value to be stored and a clock signal that indicates when the latch should read the value on the data input and store it. The outputs are simply the value of the internal state and its complement. When the clock input is asserted, the latch is said to be open, and the value of the output becomes the value of the data input. When the clock input is de-asserted, the latch is said to be closed, and the value of the output is whatever value was stored the last time the latch was open. What is the difference between DFF and D-Latch? Can one chip be used for constructing the other? Explain.Design an 8 bit calculator in assembly language using emu 8086 that perform thefollowing functionalities: Take input from user Perform 8 bit addition Perform 8 bit subtraction Display result
- The instruction that moves each bit to the right, copies the lowest bit into the Carry flag, and copies the Carry flag into the highest bit position is the one that does this.Using the following data definitions: bytel BYTE byte2 BYTE word1 WORD word2 WORD 3 OFFh, 1, 2 14h OFFFFh, 1, 2 word3 SWORD 7FFFh, 8000h word4 SWORD 9000h dword1 DWORD 10h, 20h, 30h, 40h dArray DWORD 10 DUP (?) Write an instruction that moves the lower 8 bits of word2 into the AL register.A(n) __________ is a storage location implemented in the CPU.
- A circuit which translates n input lines into a m-bit code word is defined as a * DEMUX ROM Decoder Encoder O MUX5. Load the register (CL) from the memory location [0500H] then subtract the content of this register from the accumulator (AL). Correct the result as a (BCD) numbers . Let [0500H] = 12H & AL = 3FH %3DThe outputs of four registers, A, B, C, D, H, L are connected through 8:1 line multiplexer to the input of a fifth register, X. Each register is 16 bits long. The required transfers are dictated by four timing variables, T0 through T3 as follows: T0 : X←A T1 : X←B T2 : X←C T3 : X←D The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the others are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register X.