Draw a Gantt chart showing preemptive PRIORITY schedulingand find average waiting time
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- Draw a Gantt chart showing preemptive PRIORITY schedulingand find average waiting time.
- Which of the foregoing scheduling policies provides the lowest waiting time
for this set of jobs? What is the waiting time with this policy?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?Describe the relationship between dynamic multithreading and out-of-order execution in the context of CPU design.
- Describe the concept of superscalar and out-of-order execution in modern CPU design.Superscalar processor could be a central processor that implements instruction-level correspondence inside one processor. It will execute over one instruction throughout a clock cycle. It at the same time dispatches multiple directions to completely different execution units on the processor. False TrueDiscuss the challenges involved in implementing dynamic multithreading in a CPU architecture and how they can be addressed.
- Read the given scenario and answer questions based on 8086 microprocessor architecture. A programmer has written Assembly Language Program (ALP) using 8086 instruction set. The program will read any 200 user given inputs and process them to generate 200 outputs using stack. Each input and output is a byte length data. The input values are read from memory location D217H onward and the output values are stored from memory location E106H onward. The program uses a stack and the stack is defined from the memory location 54DAH and it can store 500 values. The program has 450 instructions stored from the memory location 6E20H to 713DH. The last instruction is HLT which is a byte long instruction. Identify the segments of the given memory locations Memory Location 6EEEH Code Segment Memory Location D2D0, Data Segment Memory Location 55A2H Stack Segment What will be the value of the Instruction Pointer (IP) when the program is about to execute the 449th instruction which is of a two address…Explain out-of-order execution in the context of pipelining. How does it enhance CPU performance, and what challenges does it pose?The difference between scalar and superscale CPUs can be seen in practice. It's not surprising that the time it takes to complete superscalar processing has a strong correlation with how complicated it is. There are a few issues with the superscalar processor that must be addressed without delay.
- NOTE: "Exekveringstid(ms)" means execution time or burst time in milliseconds Assume that a system with a CPU at one time has the following processes queued in the CPU's READY queue: Calculate the waiting time for the seven processes: 1) If FCFS is being used 2) If LRU is being used 3) If RR with time quantum of 8msIn computer architecture, SIMD may refer to the situation where... a) multiple CPU cores can access the same memory concurrently. b) the same operation can be applied to multiple operands with only a single instruction. c) multiple independent instructions can be executed at the same time in the same CPU core. d) multiple independent memory banks show up as a single address space.One machine uses a 2 GHz clock and executes a program with 4 classes of instructions, A, B, C, D. Their respective cycles/instruction are CPIA=3, CPIB=2, CPIC=4, and CPID=2. Another machine has a faster clock of 3.2 GHz, and a different architecture, such that the same classes of instructions have CPIA=2, CPIB=2, CPIC=3, and CPID=2. Both machines execute a program where the frequency of the four classes of instructions is 30% for Class A, 20% for Class B, 10% for Class C and 40% are instructions of Class D. a. How many instructions did each of the machines execute in 10 seconds (assume no overhead)? b. If a program has 10º instructions, which machines finishes first? c. Which machine is more performant? d. Compare the MIPS of the two machines.