i) The instruction, MOV DX, DI+3412H is an example of: b) Based Addressing Mode 2) The machine code of the instruction (MOV [BPI|DI+ 3412H, ABH) is. a) Based-Indexed Addressing Mode e) immediate addressing mode d) Indexed Addressing Mode a) C6831234ABH b) C783BA1234H c) C683AB1234H d) C6831234BAH 3) After the execution the instruction CMP AL, 85H (when AL=7AH), the status flags will be: a) AF-1, CF 0, OF-0, PF-0, SF-0 and ZF-1 4) When the content of registers: CS-1234H, IP 0006H, SS- ABCDH and SP-AA00H. The bottom of stack is -- - and the end of stack is-- - a) 12346h b) AF-0, CF-1, OF=1, PF-1, SF-1 and ZF-0 c) AF-0, CF-1, OF-0, PF-1, SF-1 and ZF-0 d) None of the mentioned B66D0H b) AACDOH AB006H c) BBCCEH ABCDOH d)ABCDOH BBCCEH

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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1) The instruction, MOV DX, [DI]+3412H is an example of:
a) Based-Indexed
Addressing Mode
b) Based Addressing
d) Indexed Addressing
c) immediate
addressing mode
2) The machine code of the instruction (MOV (BP||DIJ+ 3412H, ABH) is.
c) C683AB1234H
Mode
Mode
а) С6831234АВН
b) C783BA1234H
d) C6831234BAH
3) After the execution the instruction CMP AL, 85H (when AL=7AH), the status flags will be:
b) AF=0, CF=1,
OF=1, PF=1,
a) AF=1, CF-0,
OF-0, PF-0, SF-0
and ZF-1
4) When the content of registers: CS-1234H, IP-0006H, SS= ABCDH and SP-AA00H. The bottom
c) AF=0, CF=1,
OF-0, PF=1, SF=1
and ZF-0
d) None of the
mentioned
SF-1 and ZF-0
of stack is ---------- and the end of stack is----
a) 12346h B66D0h b) AACDOH AB006H c) BBCCEH ABCDOH d)ABCDOH BBCCEH
5) s086 computer system using 24MHZ crystal oscillator, the duration of the bus cycle of system is -
------, and the word writing time to the memory address AAACSH is-----
c) 500ns
6) After the execution the far jump instruction JMP B3000123H, the new value of Physical Address=-
a) 41ns
82ns
b) 41ns
41ns
500ns
d) 500ns 1000ns
(if updated Physical Address=10005h)
b) вз123H
a) С3128H
7) When a data word is writing to the memory address F356CH, the state of the control signal which
occur in this cycle:
a) BHE-0, A0-1,
M/IO-0, DT/R=0,
RD 0, WR-1,
DEN-0
8) After execution the far process call instruction CALL 11000002H, the last values store in the stack
c) B3000H
d) 00123H
b) BHE-1, A0=1,
M/I0-0, DT/R=1,
RD-1, WR-0,
DEN-0.
c) BHE-1, A0-1,
M/IO-1,
DT/R-0, RD-1,
WR-0, DEN-1
d) None of the
mentioned
respectively. (if the updated value of CS:IP =(1000:0005))
c) 11 00 00 05h
are
d) 11 00 00 07h
a) 11 00 00 02h
9) Intel® producing many types of processors with dada width bus: 16-bit, 32-bit, and 64-bit data bus.
Examples of each type are:
b) 10 00 00 05h
- respectively
a) 80286, Pentium II, b) 8080, 80386, Core i9 c) 8088, 8086,
Core 2 Duo
10) When the current values of the SS register =3000H and SP register = FFDOH, The data currently
held in the stack are:
d) 80486, Pentium 4,
Core i7
Core i5.
a) 64 words
b) 32 words
c) 24 words
d) 16 words
Transcribed Image Text:1) The instruction, MOV DX, [DI]+3412H is an example of: a) Based-Indexed Addressing Mode b) Based Addressing d) Indexed Addressing c) immediate addressing mode 2) The machine code of the instruction (MOV (BP||DIJ+ 3412H, ABH) is. c) C683AB1234H Mode Mode а) С6831234АВН b) C783BA1234H d) C6831234BAH 3) After the execution the instruction CMP AL, 85H (when AL=7AH), the status flags will be: b) AF=0, CF=1, OF=1, PF=1, a) AF=1, CF-0, OF-0, PF-0, SF-0 and ZF-1 4) When the content of registers: CS-1234H, IP-0006H, SS= ABCDH and SP-AA00H. The bottom c) AF=0, CF=1, OF-0, PF=1, SF=1 and ZF-0 d) None of the mentioned SF-1 and ZF-0 of stack is ---------- and the end of stack is---- a) 12346h B66D0h b) AACDOH AB006H c) BBCCEH ABCDOH d)ABCDOH BBCCEH 5) s086 computer system using 24MHZ crystal oscillator, the duration of the bus cycle of system is - ------, and the word writing time to the memory address AAACSH is----- c) 500ns 6) After the execution the far jump instruction JMP B3000123H, the new value of Physical Address=- a) 41ns 82ns b) 41ns 41ns 500ns d) 500ns 1000ns (if updated Physical Address=10005h) b) вз123H a) С3128H 7) When a data word is writing to the memory address F356CH, the state of the control signal which occur in this cycle: a) BHE-0, A0-1, M/IO-0, DT/R=0, RD 0, WR-1, DEN-0 8) After execution the far process call instruction CALL 11000002H, the last values store in the stack c) B3000H d) 00123H b) BHE-1, A0=1, M/I0-0, DT/R=1, RD-1, WR-0, DEN-0. c) BHE-1, A0-1, M/IO-1, DT/R-0, RD-1, WR-0, DEN-1 d) None of the mentioned respectively. (if the updated value of CS:IP =(1000:0005)) c) 11 00 00 05h are d) 11 00 00 07h a) 11 00 00 02h 9) Intel® producing many types of processors with dada width bus: 16-bit, 32-bit, and 64-bit data bus. Examples of each type are: b) 10 00 00 05h - respectively a) 80286, Pentium II, b) 8080, 80386, Core i9 c) 8088, 8086, Core 2 Duo 10) When the current values of the SS register =3000H and SP register = FFDOH, The data currently held in the stack are: d) 80486, Pentium 4, Core i7 Core i5. a) 64 words b) 32 words c) 24 words d) 16 words
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