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- Design a 1-bit subtraction circuit. This circuit takes three inputs-two binary digits a and b and a borrow digit from the previous column. The circuit has two outputs-the difference (a – b), including the borrow, and a new borrow digit that propagates to the next column. Create the truth table and build the circuit. This circuit can be used to build N-bit subtraction circuits.Task 3: Design of 4-to-1 line Data Selector / Multiplexers: A multiplexer (MUX) is a combinational circuit that selects binary information from one of many input lines and directs the information to a single output line. The selection of a particular input line is controlled by a set of input variables called selection inputs. Normally, there are 2n input lines and n selection inputs whose bit combinations determine which input is selected. 4-to-1 Do MUX y D, a) Complete the truth table of the 4-to-1 line multiplexer. SELECTION INPUT OUTPUT SO $1 Y 1 1 b) Draw the 4-to-1 multiplexer logic circuit.Build a circuit that takes four bits as input: W, X, Y, Z. Treat WX as a 2-bit unsigned binary number, and treat YZ as a second 2-bit unsigned binary number. Your circuit should generate the output corresponding to the product of WX and YZ. You will need 4 bits of output for this problem.For example, if your input was 1011, your inputs correspond to 2 and 3. That product is 6, so your output will be 0110.Create a truth table for this problem, show all k-maps and minimizations, and build the corresponding (minimized) circuit. Use XOR, XNOR, NAND, and NOR as appropriate if it reduces the number of gates used.
- Design a circuit using a Multiplexer, (((USING A MULTIPLEXER NOT A DECODER))) that has two inputs X, and S, where X represents an 8-bit BCD number,S is a sign bit. The circuit has one output Y, which is the Binary representation of thesigned-magnitude BCD number. A negative output is represented in the Binary 2’scomplement form.3. Implement a BCD to seven segment decoder for a common anode seven segment display. (It means that sending a 0 to a particular segment turns on and sending a 1 turns off the corresponding LED segment of the seven segment display). Use the variables A,B,C,D for the BCD inputs with 'A' as MSB. Use only 2-4 decoders and OR gates to implement the code converter. Don't use any other gates and/or components8. For the K-map below, ONLY write the simplified expression, and then draw the simplest possible circuit. yz 00 01 11 10 00 1 1 WX 01 1 11 10 1
- Q19/ a combinational circuit has four inputs (A, B, C, D), which represent a binary- coded- decimal digit. The circuit has two groups of four outputs S, T, U, V, and W, X, Y, Z each group represents a BCD digit. The output digits represent a decimal number which is 1 more than four times the input number. For example if ABCD=0011, the output are 0001 0011. Assume that invalid BCD digits do not occur as inputs. a- Construct the truth table b- Write minterms and max terms for all output C- Find SOP and POS for all outputDraw a 4-input adder for single-bit values: that is, a set of logic gates with 4 input wires each representing a number between 0 and 1 and a multi-bit output z, composed of wires z0 through z... (where z0 is the low-order bit, z1 the next, etc., up to the number of wires needed for this task). The gates should ensure that z = the sum of all four inputs.In designing of a binary counter with states A (MSB) and B (LSB), the derived input equations are as follows TA = BOx and TB =1. Where x is input. When x = 0, the counter counts O a. AB: 11 -->10 --> 01 --> 00 -->11 O b. AB: 11--> 01 -->10 --> 00 --> 11 6 O C. AB: 00 --> 01--> 10 --> 11 --> 00 O d. AB: none of these
- b) A Decoder is a combinational circuit that converts binary information from n inputs lines to a maximum of 2" unique output lines. You have been hired by a company that manufactures printers to design a 3 x 8 Decoder for it. Design the Decoder.Design a 2-bit binary full-adder circuit using a true-output decoder. Assume carry input of the 2-bit binary full-adder is zero. Circuit adds two 2-bit binary numbers A, consisting of bits A1, AO, and B, consisting of bits B1, BO. The sum that is produced by the adder circuit consists of two sum bits S1, SO and a carry out bit CO. Provide:i. Boolean equations for S1, SO and Co.ii. Completely labelled logic diagram of decoder that implements the required operation. (You can represent the decoder in form of block diagram)Q1.Write a Verilog code for the 16 bit ripple carry adder. The hierarchy of 16 bit ripple carry adder is shown in figure below. The ripple carry adder is made up of four 4 bit full adder, each 4-bit full adder is made up of four full adders which in turn made up of two half adders and OR gate. Finally each half adder is made of xor, nand and nor gate.