Problem 2: Working with Digital Circuits Consider the function: F(x,y,z) = xy+z' . a. Draw the logical diagram of F. b. Using only NAND gates, represent F. c. Draw the minimized logical representation of the function F found in part b.
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- Construct a gate circuit using AND, OR, and NOT gates that corresponds one to one with the following switching algebra expression. Assume that inputs are available only in uncomplemented form. (Do not change the expression.) (WX' + Y)[(W + Z)' + (XYZ')]The only function of a not gate is to …..A. stop a signalB. re-complement a signalC. invert an output signalD. act as a universal gated) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.
- 5- Determine an alternative method for implement the full-adder. Hint: Write the expressions of the circuit and simplify using icarnaugh map.Then implement using AND-OR gates. 6- Design a logic cct using NAND gate and convert BCD code to Excess-3code.(a) Consider the flipflop circuits below: (i) Name the 2 circuits given in the figure. Explain how they are different from each other. a. b. (ii) Choose from the list the input that triggers data to travel to the next flipflop in a counter. A: Input at top NAND gate B: Input at bottom NAND gate C: Clock input clk QQuestion 3: PLDS & Gate Delay 1. Consider the below PAL. Find the logic expression of the outputs W, X and Y. Do not simplify. **
- Q1) For the circuits shown in figures 1 and 2: 1. What is the function of output? 2. Find the max. and min. Vol. value? 3. Determine the static power (avg.)? 4. Design equivalent logic circuit by CMOC logic circuits? Use VDD= 10 V. Vr.o=1V. Vru-1V. (W/L)o= (5/2), (W/L)L (20/2), RD = 40k, KL = 10P A/V^2 and KO = 40pA/V`2? Figure 1 5 VDD RD Figure 2 बदना दे1. Write the TTL level of the following voltages (low, high, intermediate). 2.5 . 0.3 . 4.6 . 1.1.. 3.2. ........ 2. .are complete circuits constructed on a chip of semiconductor material. What is the 3 common types of integrated circuits? . describes data shifted manually, .. describes data shifted automatically for 8 bit shift register. 3. How serial and parallel data shifted into 8 bit shift register?TRUE/FALSE QUIZ 1. The de supply voltage for TTL is typically +5 V. 2. The fan-out of a logic gate is the number of gates in an IC package. 3. CMOS uses MOSFETS. 4. BJT stands for binary junction transistor. 5. An open-collector gate must be connected to an external resistor. 6. CMOS is the dominant digital IC technology. 7. A totem-pole output means that two or more resistors are in series. 8. CMOS is subject to ESD. 9. A tri-state output can be HIGH, LOW or high-impedance. 10. Propagation delay is a measure of the speed of a logic gate.
- For the basic TTL gate shown in figure (5), if all the inputs are high at logic (1), BR = 0.02 and Br = 100, then find the value of: Note: (Write the equations of each point not just the value) 1) IB2 = Amperes. 2) Vc2=1 3) Ic2= Amperes. 4) IIKQ = 5) IB3 = Amperes. 6) Ic3 = Amperes. Volt. Amperes. Figure (5) 1.4k 4k 0₂ YQ1. Read the following description concerning a logic circuit, and then answer Subquestions 1 and 2. Figure 1 shows a logic circuit that is used as a control system for an electronic device. The logic circuit has three inputs (X, Y and Z) and one output (F). As shown in Figure 1, the logic circuit has a feed back line, by which the last output F is fed back and is used as the current input to the NAND gate. Therefore, the current output F is determined by three current inputs X, Y and Z and the last output F. In this control system, among three inputs X, Y and Z, at most only one input can change its value on each clock cycle. (Feed back line) Figure 1 The logic circuit Meanings of the logic gate symbols used in Figure 1 are as follows: AND gate NAND gate OR gate NOR gate Figure 2 shows sample input/output status of the logic…(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).