Question 1 Given the logic expressions for a set of digital circuits with four inputs (a, b, c, and d) and three outputs (F, G and H): a) Use K-map to simplify the expression for output F only and write down the logic expression in SOP. Implement the circuit using only NAND gates. b) Use VEM (variable entered mapping) to simplify the expressions for output G only. Draw the VEM K-map and write down the reduced logic expression. You are to use the least significant bit (d) as your variable. Implement the circuit using any gates of your choice. c) Use the Quine-McCluskey method to simplify the expression for output H only, and write down the logic expression. Implement the circuit using only 2:1 mux devices. d) Implement the circuits for all three outputs (F, G and H) using three 8-1 mux devices (in one diagram). [61] Hints: please show all your working and justify how you get your results No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input abed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Outputs F G 1110 1111 0 0 1 0 0 1 0 X 0 1 X X 1 1 X X 0 1 0 H 0 X 1 0 0 1 X 1 0 1 1 0 0 X 0 1 1 X 0 0 Molo 1 0 0 7. 1 0 1 0

Question 1 Given the logic expressions for a set of digital circuits with four inputs (a, b, c, and d) and three outputs (F, G and H): a) Use K-map to simplify the expression for output F only and write down the logic expression in SOP. Implement the circuit using only NAND gates. b) Use VEM (variable entered mapping) to simplify the expressions for output G only. Draw the VEM K-map and write down the reduced logic expression. You are to use the least significant bit (d) as your variable. Implement the circuit using any gates of your choice. c) Use the Quine-McCluskey method to simplify the expression for output H only, and write down the logic expression. Implement the circuit using only 2:1 mux devices. d) Implement the circuits for all three outputs (F, G and H) using three 8-1 mux devices (in one diagram). [61] Hints: please show all your working and justify how you get your results No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input abed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Outputs F G 1110 1111 0 0 1 0 0 1 0 X 0 1 X X 1 1 X X 0 1 0 H 0 X 1 0 0 1 X 1 0 1 1 0 0 X 0 1 1 X 0 0 Molo 1 0 0 7. 1 0 1 0

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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