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Referring to the timing diagram of Fig. 3-38, suppose that you slowed the clock down to a period of 20 nsec instead of 10 nsec as shown but the timing constraints remained unchanged. How much time would the memory have to get the data onto the bus dur- ing T, after MREQ was asserted, in the worst case?

Referring to the timing diagram of Fig. 3-38, suppose that you slowed the clock down to a period of 20 nsec instead of 10 nsec as shown but the timing constraints remained unchanged. How much time would the memory have to get the data onto the bus dur- ing T, after MREQ was asserted, in the worst case?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Home Tools SEC. 3.4 Φ ADDRESS DATA MREQ RD WAIT 6.37 x 9.22 in TAD Symbol TAD TML TM TRL TDS CSCI 350 Book.pdf x TMH TRH Тон -T₁ -TML- + TM TRL 193 (218 of 801) CPU CHIPS AND BUSES M Read cycle with 1 wait state -T₂² Memory address to be read Parameter Time (a) 137% Address output delay Address stable prior to MREQ MREQ delay from falling edge of in T₁ RD delay from falling edge of in T₁ Data setup time prior to falling edge of MREQ delay from falling edge of in T3 RD delay from falling edge of in T3 Data hold time from negation of RD (b) TDS Min 2 2 0 -T3· Data ||| TMH 3 3 3 3 TRH Тон : Max Unit 4 nsec nsec ●●● nsec nsec nsec nsec nsec nsec 193 2 Sign In ↓ Po Cue |→ Home Tools CSCI 350 Book.pdf x 6.37 x 9.22 in 239 (264 of 801) M 122% 25. Referring to the timing diagram of Fig. 3-38, suppose that you slowed the clock down to a period of 20 nsec instead of 10 nsec as shown but the timing constraints remained unchanged. How much time would the memory have to get the data onto the bus dur- ing T3 after MREQ was asserted, in the worst case? 2 Sign In 03 ↓ lu |→
Transcribed Image Text:Home Tools SEC. 3.4 Φ ADDRESS DATA MREQ RD WAIT 6.37 x 9.22 in TAD Symbol TAD TML TM TRL TDS CSCI 350 Book.pdf x TMH TRH Тон -T₁ -TML- + TM TRL 193 (218 of 801) CPU CHIPS AND BUSES M Read cycle with 1 wait state -T₂² Memory address to be read Parameter Time (a) 137% Address output delay Address stable prior to MREQ MREQ delay from falling edge of in T₁ RD delay from falling edge of in T₁ Data setup time prior to falling edge of MREQ delay from falling edge of in T3 RD delay from falling edge of in T3 Data hold time from negation of RD (b) TDS Min 2 2 0 -T3· Data ||| TMH 3 3 3 3 TRH Тон : Max Unit 4 nsec nsec ●●● nsec nsec nsec nsec nsec nsec 193 2 Sign In ↓ Po Cue |→ Home Tools CSCI 350 Book.pdf x 6.37 x 9.22 in 239 (264 of 801) M 122% 25. Referring to the timing diagram of Fig. 3-38, suppose that you slowed the clock down to a period of 20 nsec instead of 10 nsec as shown but the timing constraints remained unchanged. How much time would the memory have to get the data onto the bus dur- ing T3 after MREQ was asserted, in the worst case? 2 Sign In 03 ↓ lu |→
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