Show your solutions clearly and systematically. The D latch of Figure 1 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. -0 En D Next state of Q 0X 10 No change Q-0 reset state Q-1; set state 11 (a) Logic diagram (b) Function table Figure 1: D Latch 3. Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Figure 1 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output). 3

Electric Motor Control
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Chapter22: Sequence Control
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Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Show your solutions clearly and systematically.
The D latch of Figure 1 is constructed with four NAND gates and an inverter.
Consider the following three other ways for obtaining a D latch. In each case,
draw the logic diagram and verify the circuit operation.
D
En D
Next state of Q
En
0X
No change
10
11
Q = 0; reset state
Q-1; set state
(a) Logic diagram
(b) Function table.
Figure 1: D Latch
3. Use four NAND gates only (without an inverter). This can be done by
connecting the output of the upper gate in Figure 1 (the gate that goes
to the SR latch) to the input of the lower gate (instead of the inverter
output).
Q
3
Transcribed Image Text:Show your solutions clearly and systematically. The D latch of Figure 1 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. D En D Next state of Q En 0X No change 10 11 Q = 0; reset state Q-1; set state (a) Logic diagram (b) Function table. Figure 1: D Latch 3. Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Figure 1 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output). Q 3
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