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- Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?(A) Find the phicycal address if (BP) = 0100H , (SI) = 0200H , (SS) = 2000H and a displacement of 10H, of the instruction MOV AL , [BP+SI+10H]. Which the name of Addressing Modes? (B) Find the result of the following: 1111 - 1111H+ 110010111011BSuppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 210 ps and a CPI of 2.2 for some programs, and computer B has a clock cycle time of 460 ps and a CPI of 1.3 for the same program. Which computer is faster for this program and by how much? Please and thank you
- 2. Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much?Two interrupts have execution times of 7.5us and 10 us. Both occur at the same rate, Find the maximum frequency that they can occur to maintain a combined CPU% less than 1.5%?Computer Science Consider that the processor fetches the following instruction word: 00010001000101011111111111110001 Assume that the initial values of GPRs are the same as their register numbers. Q). What are the outputs of the sign-extend and its subsequent “Shift left 2” unit for this instruction word?
- Write an instruction to sum of the values 9AH, 29H and F4H.Put the sum in registers RO (low byte) and R7 (high byte). (C5) Find the time delay for the delay subroutine shown to the right, if the system has an 8051 with frequency of 11.0592 MHz (C4) DELAY: AGAIN: MOV R2, #150 MOV R3, #250 NOP NOP NOP DJNZ R3, HERE DJNZ R2, AGAIN RETDo you know what would happen if an instruction was rejected? When compared to a hardware-managed TLB, a software-managed TLB is quicker in the following scenarios:Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (.(Note: all numbers are in Hexadecimal The content of IR after the end of execution :for the next instruction is 4620 O 9473 5431 None of the choices 7010 O
- Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in Hexadecimal.) p 4:33 The content of AC after the end of * :execution for the next instruction is 700 O 620 320 O None of the choices O 4:35 /In this case, every instruction receives its own data, independent of how the data for other instructions is obtained. We make advantage of a: A Multiple Data/Instruction B Multiple Iterations of Data or Instruction C Singular Data Single Inst D Singe Inst Multiple2. An implementation of the above RISC-V microprocessor has been designed where the supported instructions are classified as follows with regard to the number of cycles required to execute: Arithmetic & Logic: 4 cycles Memory Access: 5 cycles 3 cycles Branching: System Calls: 1 cycle What is the average CPI for this microprocessor? (includes lui, add, addi, or, ori, sub, and, (includes all loads and stores) (includes blt, beq, bne) (includes ecall) andi)