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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
- A processor with clocking rate of 8MHZ need to execute 3 instruction, where for each instruction the microprocessor need to scan the Input or Output device at every 12 clock cycle. (a) Calculate the time taken to perform 1 clock cycle. (b) Calculate the time taken to scan the Input Output device for each instruction.If a pipelined CPU has a pipeline depth of 7, how many sets of pipeline registers will it have?A processor with clocking rate of 8MHz need to execute 3 instruction, where for each instructionthe microprocessor need to scan the Input or Output device at every 12 clock cycle. (a) Calculate the time taken to perform 1 clock cycle.(b) Calculate the time taken to scan the Input Output device for each instruction.(c) Calculate the time taken to execute 3 instructions.
- Two processors A and B have clock rate of 700 MHz and 900 MHz respectively. Suppose A can execute an instruction with an average CPI equal to 3 and B can execute with an average CPI of 5. For the execution of same instruction, which processor is faster? Select one: a. Both are equally fast O b. B c. None O d. AQuestion 1: Answer the following questions: 1. Make the internal block diagram of a Central Processing Unit (CPU) 2. Write down the steps of execution of an instruction 3. If each step takes 3 nS, then what will be the length of clock cycle? 4. What will be the length of execution of one instruction? 5. If there are 10000 instructions, what will be the total time of execution?Describe the stages of instruction pipelining in a typical CPU architecture. What are the potential hazards or bottlenecks in a pipeline?
- 1. How to improve CPU performance under same Instruction Set Architecture following three ways: i. Clock rate improvement 1. Reduce CPI 11. Reduce instruction count Please list a factor for each of the ways mentioned above that affects them.When comparing pipelined and non-pipelined CPUs, the former has a faster clock cycle time.Describe the stages of instruction pipelining in a typical CPU. How does it affect instruction execution time?