The Intel80486 has on-chip, unified cache. It contains 8Kbytes and has a four way set associative organization and a block length of four 32-bit words. The cache is organized into 128 sets. There is a single “line valid bit” and three bits,B0,B1,B2 (the LRU bits) per line. On a cache miss, the 80486 reads a 16 byte line from main memory in a bus memory read burst. Show the details for the different fields of the address.

The Intel80486 has on-chip, unified cache. It contains 8Kbytes and has a four way set associative organization and a block length of four 32-bit words. The cache is organized into 128 sets. There is a single “line valid bit” and three bits,B0,B1,B2 (the LRU bits) per line. On a cache miss, the 80486 reads a 16 byte line from main memory in a bus memory read burst. Show the details for the different fields of the address.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 30VE

See similar textbooks

Similar questions

In a Direct Mapped Cache Memory Physical Address format the Cache line offset field size and word offset field size are same (with word size of one Byte). The number of tag bits in the Physical Address format is equal to the number of blocks in Cache Memory. If the Tag field Size is Mega words. 16 bits, the size of the physical Memory is
A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?
6- In 8086Mp bus cycles, the signal (ALE) becomes '1' during clock cycle. 7- The type of the buffer used for buffering data lines is while the type of the buffer used for buffering address lines is 8- During transferring a data of 8-bits from 8086Mp to memory address (1F871H), give the logic value of the following signals: M/IO= RD= = WR= BHE= 9- The benefit of multiplexing operation is 1. CC
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?
The address bus consists parallel signal lines while data bus consists separate lines. True O False Hardwired control units are generally faster than micro - programmed designs. * True False The main property of a bus is that it is a shared transmission medium. * True O False
You are given a main memory of 64Mbytes with each byte addressable and asked to design a cache memory using direct mapping. The main memory is organized as blocks of 8bytes. The cache memory must have a size of 512Kbytes. What should be the size of the tag in bits?
Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?
In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.
You are given a main memory of 64Mbytes with each byte addressable and asked to design a cache memory using direct mapping. The main memory is organized as blocks of 8bytes. The cache memory must have a size of 512Kbytes. How many lines do you need to use in the cache memory?
A computer employs RAM chips of 512 x 4 and ROM chips of 256 x 8. The computer system needs 1KB of RAM, and 512 x 8 ROM and an interface unit with 256 registers each. A memory-mapped I/O configuration is used. The two higher -order bits of the address bus are assigned 00 for RAM, O1 for ROM, and 10 for interface. a) How many lines must be decoded for chip select? Specify the size of the decoder b) Draw a memory-address map for the system and Give the address range in hexadecimal for RAM, ROM c) Develop a chip layout for the above said specifications.
A virtual address of 32 bits is passed on to the TLB. If the number of entries (number of cache lines) in the TLB are 32, what is the width of the Tag field in the TLB?
The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions will be ?