(Z1 and Z2). The inputs represent a 2-bit binary number (N). If the present value of (N) plus the previous value of (N) is greater than (2), then (Z1=1). If the present value of (N) times the previous value of (N) is greater than (2), then (Z2=1). Otherwise, (Z1Z2=00). When the first pair of inputs is received, use (0) as the previous value of (N). The circuit of the *.aforementioned state machine includes . AND-gates
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- H.W :- 1) A four logic-signal A,B,C,D are being used to represent a 4-bit binary number with A as the LSB and D as the MSB. The binary inputs are fed to a logic circuit that produces a logic 1 (HIGH) output only when the binary number is greater than 01102-610. Design this circuit. 2) repeat problem 1 for the output will be 0 (LOW) when the binary input is less than 01112-710- Saleem LateefA synchronous state machine has two inputs (X1 and X2) and two outputs (Z1 and Z2). The inputs represent a 2-bit binary number (N). If the present value of (N) plus the previous value of (N) is greater than (2), then (Z1-1). If the present value of (N) times the previous value of (N) is greater than (2), then (Z2=1). Otherwise, (Z1Z2=D00). When the first pair of inputs is received, use (0) as the previous value of (N). The minimal Mealy state diagram of the aforementioned state machine includes ... * .states 9:10 صDesign a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.
- How many states required to design an FSM machine to process the following sequence, 000111000 6. 6. 3Up/Down State Machine Cousider a state machine implementation of a two bit up/down counter mput: up/doun, and two outputs: Outo and Out,, which also indicate the next state. When up/dowTI is high, the counter counts up (00,01,10,11,00, ). When up/doun is low, the counter counts down (00,11.10.01.00, ..). The state machine has one Part A Complete the state diagram below by adding all required transition arcs with input annotations. Output annotations are not required since they correspond to the new state. state state 00 01 state state 10 11Draw a state diagram for: Mealy state machine to detect the 1010 sequence. The output becomes one when you receive the sequence of 1100 and the output is zero otherwise. Overlap is allowed between the detected sequences.
- Design a combinational circuit with 3-inputs and 1-output. The output is equal to logic-1 when the binary value of the input is less than 3. And the output is logic-0 otherwise.(b) Using a synchronous binary counter as shown in Figure Q2(b), design and draw a counter to generate the following repeating sequences 2 to 14 repeatedly for a free running clock. If the circuit happens to enter any of the states 15 or 0 or 1, what are the next states of your circuit? A A Syn. Binary Counter Q3 Q2 Q₁ Qo →Asyn. clear Syn. load CLK D3 D₂ D₁ Do ↑↑↑↑Which function performs the following operation? Give the assembly instruction and show your work. Before A= 11011011, CF=1 After A= 10111101, CF=1
- Design the interfacing circuit shown below and write a program to display single digit (between 0 and 9) prime numbers followed by even numbers, the next odd numbers and repeats in 7-segment displays and its equivalent 8-bit binary value in LEDS. a) When displaying Prime numbers, the first 7-segment display must show "P" and the second 7-segment display must show prime numbers one by one b) When displaying Even numbers, the first 7-segment display must show "E" and the second 7-segment display must show even numbers one by one c) When displaying Odd numbers, the first 7-segment display must show "O" and the second 7-segment display must show even numbers one by oneUSE DIGITAL LOGIC AND DESIGN Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW. A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110 Figure_4 Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3. Figure_5 Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input. Figure_6 Part 4: The data-input and…(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).